DocumentCode :
3260895
Title :
Temperature-aware routing in 3D ICs
Author :
Zhang, Tianpei ; Zhan, Yong ; Sapatnekar, Sachin S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
fYear :
2006
fDate :
24-27 Jan. 2006
Abstract :
3D integrated circuits (3D ICs) provide an attractive solution for improving circuit performance. Such solutions must be embedded in an electrothermally-conscious design methodology, since 3D ICs generate a significant amount of heat per unit volume. In this paper, we propose a temperature-aware 3D global routing algorithm with insertion of "thermal vias" and "thermal wires" to lower the effective thermal resistance of the material, thereby reducing chip temperature. Since thermal vias and thermal wires take up lateral routing space, our algorithm utilizes sensitivity analysis to judiciously allocate their usage, and iteratively resolve contention between routing and thermal vias and thermal wires. Experimental results show that our routing algorithm can effectively reduce the peak temperature and alleviate routing congestion.
Keywords :
integrated circuit interconnections; integrated circuit layout; network routing; thermal analysis; 3D global routing algorithm; 3D integrated circuits; electrothermal design methodology; temperature-aware routing; thermal resistance; thermal vias; thermal wires; Circuit optimization; Design methodology; Electrothermal effects; Iterative algorithms; Routing; Sensitivity analysis; Temperature sensors; Thermal resistance; Three-dimensional integrated circuits; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Print_ISBN :
0-7803-9451-8
Type :
conf
DOI :
10.1109/ASPDAC.2006.1594700
Filename :
1594700
Link To Document :
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