A MPEG decoder ASIC for compact disc interactive

An ASIC was designed to implement an MPEG decoder. This resulted in a 140000 gate-equivalent design, which worked first time around. This chip contains a decoder, a video generator with window control and a system controller that interfaces with a 68000 environment. A new approach to simulation is developed to speed up the simulations. The chip is translated to a software model. This software model is compiled into an executable file, with the `simulator´ built in. The software model was about 1000 times faster than the chip level simulator. This made it possible to simulate the chip extensively in very short time