Title :
Threshold-Voltage Modeling of Bulk FinFETs by Considering Charge-Sharing and Surface Potential
Author :
Lee, Jong-Ho ; Choi, Byung-Kil
Author_Institution :
Senior Member, IEEE, School of EECS, Kyungpook National University, Sangyuk-Dong, Buk-Gu, Daegu, Korea (ROK), 702-701
Abstract :
The threshold voltages (Vth) of the double/triplegate bulk FinFETs implemented on bulk silicon wafers were modeled systematically and compared with data obtained from 2-D or 3-D device simulation. The Vth modeling of the bulk FinFETs was performed by considering charge-sharing, top corner effect, and surface potential lowering. The model predicted the Vth behavior with fin body thickness, body doping concentration, gate length, gate height, and corner shape of the fin body well. Our compact model made an accurate Vth prediction of the devices with the gate length up to 20 nm and the fin body width up to 5 nm.
Keywords :
CMOS technology; Doping profiles; FinFETs; Mercury (metals); Predictive models; Semiconductor device modeling; Semiconductor process modeling; Shape; Silicon; Threshold voltage; Bulk FinFET; corner effect; modeling; narrow-width effect (NWE); short-channel effect (SCE); surface potential lowering; threshold voltage;
Conference_Titel :
Electron Devices and Semiconductor Technology, 2007. EDST 2007. Proceeding of 2007 International Workshop on
Conference_Location :
Tsinghua University
Print_ISBN :
1-4244-1098-3
Electronic_ISBN :
1-4244-1098-3
DOI :
10.1109/EDST.2007.4289770