A transpose-register for a 2D-FFT of 64×64 pixel-blocks

The transpose-register is part of a system for data reduction of digital HDTV-signals. This approach is leading to a single-chip solution for the luminance signal. The algorithm implemented is based on two-dimensional transform coding of large subblocks. Using the two-column approach for two dimensional (2D) FFT, a transpose-register performing a read- and a write-access for 2048 bit in μsec is required. The size of the transpose-register is 131072 bit (128*64*16 bit). Register-cycle-time is 80 nsec for read or write of 512 bit (=6.4 Gbit/s) of an image-block-row or column. Thus row and column access-mode is implemented by a dual-port memory-cell plus horizontal and vertical bit-lines. Using a 1.5 μ CMOS-technology the area of the register is 128 mm² and determined by the bitlines