Title :
Context-based ASIC synthesis
Author :
Kelem, Steven H. ; Seidel, Jorge P.
Author_Institution :
Xilinx Inc., San Jose, CA, USA
Abstract :
The authors describe methods for architecture-specific mapping of high-level functions ASICs. The techniques are demonstrated on field programmable gate arrays (FPGAs), but are not limited to those architectures. A network of generic modules provides an input specification from which a delay- and area-efficient logic-level design is synthesized. The methods described herein speed up design time significantly by automatically propagating partial data type specifications, performing architecture-specific design optimizations, and performing context-dependent module synthesis
Keywords :
application specific integrated circuits; circuit CAD; digital integrated circuits; logic CAD; ASIC synthesis; FPGA; X-BLOX data; architecture-specific mapping; context based synthesis; context-dependent module synthesis; field programmable gate arrays; high-level functions; logic-level design; partial data type specifications; Application specific integrated circuits; Circuit synthesis; Design methodology; Design optimization; Field programmable gate arrays; Hardware design languages; Market research; Network synthesis; Packaging; Programmable logic arrays;
Conference_Titel :
Euro ASIC '92, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-2845-6
DOI :
10.1109/EUASIC.1992.228020
