Future of Nano CMOS Technology

Author

Iwai, Hiroshi

Author_Institution

Frontier Collaborative Research Center, Tokyo Institute of Technology, 4259, Nagatsuta-cho, Midori-ku, Yokohama, 226-8502. Phone: +81-(45) 924-5471. Fax: +81-(45) 924-5584. Email: h.iwai@ieee.org

fYear

2007

fDate

3-4 June 2007

Firstpage

57

Lastpage

61

Abstract

CMOS technology has been developed into the sub-100 nm range. It is expected that the nano-CMOS technology will governed the IC manufacturing for at least another couple of decades. Though there are many challenges ahead, further down-sizing the device to a few nanometers is still on the schedule of International Technology Roadmap for Semiconductors (ITRS). Several technological options for manufacturing nano-CMOS microchips have been available or will soon be available. This paper reviews the challenges of nano-CMOS downsizing and manufacturing. We shall focus on the recent progress on the key technologies for the nano-CMOS IC fabrication in the next fifteen years.

Keywords

CMOS technology; Humans; Insulation; Integrated circuit technology; Large scale integration; Power generation economics; Production; Random access memory; Semiconductor device manufacture; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Semiconductor Technology, 2007. EDST 2007. Proceeding of 2007 International Workshop on

Conference_Location

Tsinghua University

Print_ISBN

1-4244-1098-3

Electronic_ISBN

1-4244-1098-3

Type

conf

DOI

10.1109/EDST.2007.4289777

Filename

4289777