Title :
Schottky s/d MOSFETs with high-K gate dielectrics and metal gate electrodes
Author :
Zhu, Shiyang ; Jingde Chen ; Yu, H.Y. ; Whang, S.J. ; Chen, Jingde ; Shen, Chih-Teng ; Li, M.-F. ; Lee, S.J. ; Zhu, Chunxiang ; Chan, D.S.H. ; Du, Anyan ; Tung, C.H. ; Singh, Jagar ; Chin, Albert ; Kwong, D.L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore
Abstract :
Bulk Schottky silicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0 ∼ 2.5nm HfO2 gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi silicide show excellent electrical performance of Ion/Ioff∼ 107 - 108 and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi2-x silicide have also demonstrated a very promising characteristic with a recorded high Ion/Ioff radio of ∼ 107 and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.
Keywords :
MOSFET; Schottky barriers; Schottky gate field effect transistors; dielectric materials; semiconductor technology; silicon-on-insulator; HfN-TaN; HfO2; PtSi; Schottky s/d MOSFETs; YbSi; gate dielectric; high-K gate dielectrics; low temperature process; metal gate electrodes; metal gate materials; n-MOS transistor; p-MOS transistors; sub-tenth micron CMOS technology; ultra-thin-body SOI structures; CMOS technology; Electrodes; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Implants; Inorganic materials; MOSFETs; Silicides; Temperature;
Conference_Titel :
Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on
Print_ISBN :
0-7803-8511-X
DOI :
10.1109/ICSICT.2004.1434952
