Study of charge trapping/detrapping mechanism in SiO2/HfO2 stack gate dielectrics considering two-way detrapping

A theoretical model for analyzing the threshold voltage instability induced by charge trapping in the MOSFETs using high-k gate dielectric stacks has been developed. The focus of this work is to investigate the role of detrapped electrons to the gate, which has been taken as negligible before. A predominant role of that effect has been observed with decreasing effective oxide thickness. It has also been found that, this effect becomes non-trivial with higher trapping time.