DocumentCode
3261684
Title
Design and implementation of the data-path of a 32-bit RISC microprocessor:HRISCII
Author
El-haffaf, Youssef I. ; Bouaraoua, A. ; Amari, A.
Author_Institution
Microelectron. Lab., Centre de Dev. des Technol. Avancees, Algiers, Algeria
fYear
1992
fDate
1-5 Jun 1992
Firstpage
266
Lastpage
269
Abstract
Describes the design and the implementation of the data-path of a 32-bit RISC microprocessor called HRISCII. This unit was designed to operate with a 20 MHz clock rate, has been implemented in a 2 micron, two layers metal, one polysilicon CMOS process. It contains about 16 000 transistors and occupies an area of 20 mm2
Keywords
CMOS integrated circuits; computer architecture; microprocessor chips; reduced instruction set computing; 2 micron; 20 MHz; 32 bit; 32-bit microprocessors; CMOS; HRISCII; RISC microprocessor; area; circuit layout; clock rate; data-path; design; implementation; CMOS process; Circuits; Clocks; Computer aided instruction; Computer architecture; Microelectronics; Microprocessors; Multiplexing; Reduced instruction set computing; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Euro ASIC '92, Proceedings.
Conference_Location
Paris
Print_ISBN
0-8186-2845-6
Type
conf
DOI
10.1109/EUASIC.1992.228043
Filename
228043
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