ASIC design of a high performance RISC

Author

Lee, Moon Key ; Choi, Byeong Yoon ; Lee, Seoung Ho ; Lee, Kwang Yup

Author_Institution

Res. Inst. of ASIC Design, Yonsei Univ., Seoul, South Korea

fYear

1992

fDate

1-5 Jun 1992

Firstpage

262

Lastpage

265

Abstract

Describes the VLSI implementation of a 32-bit central processing unit (CPU) chip based on reduced instruction set computer (RISC) principles and its testing methodology based on functional fault model. The processor which adopts 4-stage instruction execution pipeline has achieved the goal of single cycle execution using a 2-phase 16.7 MHz clock. The cell-based approach was chosen as VLSI implementation scheme of SPARK RISC CPU. Performance simulation shows that this architecture achieves a scalar performance of 16.7 MIPS (million instructions per second) peak. This chip is implemented with 1.0 μm double layer metal CMOS technology and consists of about 150 K transistors

Keywords

CMOS integrated circuits; VLSI; application specific integrated circuits; microprocessor chips; pipeline processing; reduced instruction set computing; 1 micron; 16.7 MHz; 16.7 MIPS; 32 bit; 4-stage instruction execution pipeline; ASIC design; SPARK RISC CPU; VLSI implementation; cell-based approach; circuit layout; double layer metal CMOS technology; functional fault model; high performance RISC; reduced instruction set computer; scalar performance; single cycle execution; testing methodology; two phase clock; Application specific integrated circuits; CMOS technology; Central Processing Unit; Clocks; Computer aided instruction; Pipelines; Reduced instruction set computing; Sparks; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Euro ASIC '92, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-2845-6

Type

conf

DOI

10.1109/EUASIC.1992.228044

Filename

228044