Title :
A high performance 100 nm generation SOC technology (CMOS IV) for high density embedded memory and mixed signal LSIs
Author :
Miyashita, K. ; Nakayama, T. ; Oishi, A. ; Hasumi, R. ; Owada, M. ; Aota, S. ; Okayama, Y. ; Matsumoto, M. ; Igarashi, H. ; Yoshida, T. ; Kasai, K. ; Yoshitomi, T. ; Fukaura, Y. ; Kawasaki, H. ; Ishimaru, K. ; Adachi, K. ; Fujiwara, M. ; Ohuchi, K. ; Taka
Author_Institution :
Syst. LSI Div., Toshiba Corp., Yokohama, Japan
Abstract :
This paper demonstrates a 100 nm generation SOC technology (CMOS IV) for the first time. Three types of core devices are presented with optimized gate oxynitrides for their stand-by power conditions. This advanced logic process is compatible with 0.18 /spl mu/m/sup 2/ trench capacitor DRAM and 1.25 /spl mu/m/sup 2/ 6 transistor SRAM. Two kinds of high V/sub dd/ devices can be prepared by the triple gate oxide process. Moreover, for mixed signal applications, Ta/sub 2/O/sub 5/ MIM capacitors are introduced into Cu and low-k interconnects.
Keywords :
CMOS integrated circuits; DRAM chips; MIM devices; SRAM chips; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; isolation technology; mixed analogue-digital integrated circuits; nanotechnology; 100 nm; CMOS-IV SOC technology; Cu; Cu/low-k interconnects; DRAM; SRAM; Ta/sub 2/O/sub 5/; Ta/sub 2/O/sub 5/ MIM capacitors; core devices; logic process; mixed signal applications; optimized gate oxynitrides; stand-by power conditions; transistor; trench capacitor; triple gate oxide process; CMOS logic circuits; CMOS technology; Distributed power generation; Large scale integration; Logic devices; MIM capacitors; MOSFETs; Random access memory; Signal generators; System-on-a-chip;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934922
