Transient fault emulation of hardened circuits in FPGA platforms

Very deep submicron and nanometer technologies are emphasizing soft errors as an important issue in the challenges of modem electronic systems. Hardened circuits are currently required in many applications where fault tolerance (FT) was not a requirement in the very near past. Together with the generation of tools and methods for hardening circuits, new ways of validating the FT are needed. These solutions must be cost effective and provide a help not only in measuring the robustness of the circuit but also in locating the weak areas and in proposing hardening solutions. FPGA emulation of SEU effects is gaining attention in order to speed up the fault tolerance evaluation. In this work a system is proposed for the evaluation of fault tolerance with respect to SEU effects by emulation in platform FPGAs. In this system, most of the modules of a typical fault injection environment are embedded in the FPGA. Therefore, the time required for the FT validation has been optimised with respect to existing approaches.