ASIC and board design of a high performance parallel architecture

The integrated design of ASIC and board is a key approach for high performance parallel architectures. This paper describes the solutions adopted in the design of a parallel architecture for research purposes. The heart of the architecture is an ASIC processor (100 K transistors, 180 pin PGA, 30 MHz) with RISC features and instruction-level parallelism capabilities. The whole system design has been carried on within an integrated CAD framework, which has allowed a concurrent development of software (compiler), hardware (system board) and VLSI (processor) components. In particular, the authors present the aspects related to the design of the system board (3 ASICs, memory and ISA bus interface for a total of about 247 ICs and 8 interconnection layers), showing how different levels of board simulation can help to improve the quality of the design. They also detail the adopted pipelined design style, which shows some peculiarities with respect to traditional approaches