Title :
An 8-b 1-GSmaples/s CMOS Cascaded Folding and Interpolating ADC
Author :
Zhu, Xubin ; Ni, Weining ; Zhang, Qiang ; Shi, Yin
Author_Institution :
Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
Abstract :
This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-¿m CMOS technology, and measures 1.47 mm × 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.
Keywords :
Analog-digital conversion; CMOS analog integrated circuits; CMOS technology; Circuit topology; Differential amplifiers; Low voltage; Sampling methods; Switched capacitor circuits; Switches; Switching circuits; Analog-to-Digital converter; CMOS analog integrated circuit; cascading; folding-and-interpolating;
Conference_Titel :
Electron Devices and Semiconductor Technology, 2007. EDST 2007. Proceeding of 2007 International Workshop on
Conference_Location :
Tsinghua University
Print_ISBN :
1-4244-1098-3
Electronic_ISBN :
1-4244-1098-3
DOI :
10.1109/EDST.2007.4289804
