Title :
Reduction of the number of symbolic outputs of finite state machines
Author_Institution :
Forschungszentrum Informatik, Karlsruhe, Germany
Abstract :
An algorithm is presented which works on the symbolic level, prior to the code assignment phase. Under certain conditions it is possible to implement several symbolic outputs by one single symbolic output. By that, the number of symbolic outputs, and therefore, the number of binary output functions which have to be implemented is reduced. This is in particularly useful if the number of output functions which can be realized is restricted, e.g., if the controller has to be implemented by a certain type of PLA with a fixed number of output columns
Keywords :
Boolean functions; finite state machines; logic arrays; PLA; binary output functions; finite state machines; output columns; symbolic level; symbolic outputs; Automata; Circuit synthesis; Control system synthesis; Design automation; Encoding; High level synthesis; Multiplexing; Programmable logic arrays; Signal generators; Signal synthesis;
Conference_Titel :
Euro ASIC '92, Proceedings.
Conference_Location :
Paris
Print_ISBN :
0-8186-2845-6
DOI :
10.1109/EUASIC.1992.228061
