DocumentCode
3262037
Title
A memory grouping method for sharing memory BIST logic
Author
Miyazaki, Masahide ; Yoneda, Tomokazu ; Fujiwara, Hideo
Author_Institution
Graduate Sch. of Inf. Sci., Nara Inst. of Sci. & Technol. (NAIST), Ikoma
fYear
2006
fDate
24-27 Jan. 2006
Abstract
With the increasing demand for SoCs to include rich functionality, SoCs are being designed with hundreds of small memories with different sizes and frequencies. If memory BIST logics were individually added to these various memories, the area overhead would be very high. To reduce the overhead, memory BIST logic must therefore be shared. This paper proposes a memory-grouping method for memory BIST logic sharing. A memory-grouping problem is formulated and an algorithm to solve the problem is proposed. Experimental results showed that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The results also showed that the ability to select from two types of connection methods produced a greater reduction in area than using a single connection method
Keywords
built-in self test; integrated circuit testing; integrated memory circuits; logic testing; built in self test; memory BIST logic; memory BIST wrapper; memory grouping method; Built-in self-test; Circuit testing; Frequency; Information science; Logic testing; Memory management; Scheduling; Sequential analysis; Signal generators; Time factors;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location
Yokohama
Print_ISBN
0-7803-9451-8
Type
conf
DOI
10.1109/ASPDAC.2006.1594763
Filename
1594763
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