Title :
Automated logic SER analysis and on-line SER reduction
Author :
Nieuwland, André K. ; Gindner, Patrick
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
This paper presents a method for automated analysis of a combinational circuit to find the most SEU sensitive path, and proposes a way to make this path more robust for SEU in a low cost way.
Keywords :
automatic testing; combinational circuits; logic testing; probability; radiation hardening (electronics); SEU sensitive path; Verilog netlist; automated logic SER analysis; combinational circuit; figure of merit; glitch propagation probability; low cost; on-line SER reduction; optimization; Charge carrier mobility; Circuit analysis; Circuit testing; Combinational circuits; Costs; Laboratories; Logic circuits; Neutrons; Protection; Robustness;
Conference_Titel :
On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International
Print_ISBN :
0-7695-2180-0
DOI :
10.1109/OLT.2004.1319679
