ITEM: an if-then-else minimizer for logic synthesis

Introduces ITEM, the combinational logic minimization program developed at the University of California, Santa Cruz. ITEM is useful for generating highly testable circuits, because canonical if-then-else DAGs are robustly path-delay-fault testable, and often produce small, fast circuits. Several of the transformations preserve testability, including the Xmap and Amap technology mappers for field-programmable gate arrays. The paper includes the definitions of if-then-else DAGs and canonical forms, introduces a new technology mapper for table-lookup FPGAs, briefly mentions the main transformations available in ITEM, and provides a table of benchmark results for mapping to 5-input tables using various transformations. This paper also introduces a new technology mapper based on a generate-and-test paradigm