Title :
A technique to reduce power and test application time in BIST
Author :
Ghosh, Debjyoti ; Bhunia, Swarup ; Roy, Kaushik
Author_Institution :
Purdue Univ., West Lafayette, IN, USA
Abstract :
Increased switching activity during testing causes substantial increase in power dissipation. This paper presents an efficient test application procedure for reducing power dissipation in test-per-scan BIST as well as the test application time, while maintaining the fault coverage. Experiments on ISCAS89 benchmarks show promising results - up to 51.8% (63.1%) peak power reduction and an average energy saving of 36.3% (62.3%) in the combinational logic (scan chain) for three partitions.
Keywords :
boundary scan testing; built-in self test; design for testability; logic design; logic testing; DFT logic; combinational logic; fault coverage; peak power reduction; scan chain; test application time reduction; test power dissipation reduction; test-per-scan BIST; testing switching activity; Benchmark testing; Built-in self-test; Circuit faults; Circuit testing; Clocks; Energy dissipation; Logic; Multiplexing; Power dissipation; Switching circuits;
Conference_Titel :
On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International
Print_ISBN :
0-7695-2180-0
DOI :
10.1109/OLT.2004.1319684
