Title :
Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding
Author :
Huang, L.-J. ; Chu, J.O. ; Goma, S. ; D´Emic, C.P. ; Koester, S.J. ; Canaperi, D.F. ; Mooney, P.M. ; Cordes, S.A. ; Speidell, J.L. ; Anderson, R.M. ; Wong, H.-S.P.
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
N- and p-MOSFETs have been fabricated in strained Si on SiGe on insulator (SSOI) with high (15-25%) Ge content. Wafer bonding and H-induced layer transfer techniques enabled the fabrication of the high Ge content SiGe-on-insulator (SGOI) substrates. Mobility enhancement of 46% for electrons and 60-80% for holes (for 20%-25% Ge content) has been demonstrated in SSOI MOSFETs. This could lead to next generation device performance enhancement.
Keywords :
Ge-Si alloys; MOSFET; electron mobility; hole mobility; ion implantation; semiconductor device measurement; semiconductor materials; silicon-on-insulator; wafer bonding; Ge content; H-induced layer transfer techniques; SGOI substrates; SSOI; SSOI MOSFETs; Si-SiGe-SiO/sub 2/; carrier mobility enhancement; device performance enhancement; electron mobility; high Ge content SiGe-on-insulator substrates; hole mobility; n-MOSFETs; p-MOSFETs; strained Si on SiGe on insulator; strained Si-on-insulator; wafer bonding; Capacitance-voltage characteristics; Charge carrier processes; Electron mobility; Germanium silicon alloys; Insulation; MOSFET circuits; Planarization; Silicon germanium; Substrates; Wafer bonding;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934945
