DocumentCode :
3262238
Title :
Yield-preferred via insertion based on novel geotopological technology
Author :
Luo, Fangyi ; Jia, Yongbo ; Dai, Wayne Wei-Ming
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA
fYear :
2006
fDate :
24-27 Jan. 2006
Abstract :
Yield-preferred via insertion is an effective method to reduce the yield loss caused by via failures. The existing methods to apply the redundant-cut vias in metal layers are not efficient nor adequate. In this paper, we present an effective and efficient yield-preferred via insertion method based on a novel geotopological layout platform, GEOTOP. Our method chooses the most yield-favored via candidate and insert it into the layout without causing any design rule violations. Experiments with real industry designs show that our method can achieve very high rate of yield-preferred via without increasing the design die size within acceptable running time
Keywords :
integrated circuit layout; integrated circuit yield; geotopological layout; geotopological technology; yield loss; yield-preferred via insertion method; Delay; Electrons; Foundries; Integrated circuit interconnections; Integrated circuit yield; Performance loss; Routing; Thermal stresses; Very large scale integration; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-9451-8
Type :
conf
DOI :
10.1109/ASPDAC.2006.1594773
Filename :
1594773
Link To Document :
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