Accumulator based test-per-scan BIST

Arithmetic function modules, which are available in many circuits, can be utilized to generate test patterns and compact test responses. Recently, an accumulator behaving in test mode as a non-linear feedback shift register (NLFSR) has been proposed for bit-serial test pattern generation. However, this structure has the disadvantage that the maximum period of the generated bit sequence depends on the suitable selection of a constant additive value (CAV), which is based on an exhaustive trial and error procedure. In this paper, we propose a slightly modified structure and a heuristic for speeding up significantly the searching of a suitable CAV. We also show, experimentally, that the proposed structure, in most cases, compares favorably to LFSRs and the other arithmetic function based bit-serial sequence generators.