Title :
A BIST-based charge analysis for embedded memories
Author :
Alorda, B. ; Canals, V. ; De Paúl, I. ; Segura, J.
Author_Institution :
Dept. de Fisica, Univ. de les Illes Baleares, Palma de Mallorca, Spain
Abstract :
We present a BIST architecture to perform charge based analysis on embedded memories. The architecture includes a charge monitor as well as the input generation and output processing circuitry. The method applies a charge correlation technique, validated experimentally on previous works for submicron SRAMs. The technique requires a short pre-characterization phase during manufacturing testing that guarantees process-variation immunity. The embedded BIST circuitry provides a digital output pass/fail flag that signals the result of the BIST-charge analysis.
Keywords :
built-in self test; charge measurement; correlation methods; integrated memory circuits; transient analysis; BIST-based charge analysis; SRAM; built-in current monitors; charge based testing; charge correlation technique; charge monitor; digital output pass/fail flag; embedded memories; manufacturing test pre-characterization phase; process-variation immunity; transient current testing; Built-in self-test; Charge measurement; Circuit testing; Condition monitoring; Current measurement; Current supplies; Integrated circuit testing; Production; Shape measurement; Transient analysis;
Conference_Titel :
On-Line Testing Symposium, 2004. IOLTS 2004. Proceedings. 10th IEEE International
Print_ISBN :
0-7695-2180-0
DOI :
10.1109/OLT.2004.1319688
