Title :
50 nm SOI CMOS transistors with ultra shallow junction using laser annealing and pre-amorphization implantation
Author :
Cheolmin Park ; Seong-Dong Kim ; Yun Wang ; Talwar, S. ; Woo, J.C.S.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
CMOS transistors with 50 nm physical gate length are fabricated by laser annealing (LA) combined with pre-amorphization implantation (PAI) on an SOI substrate. Very low energy laser annealing is made possible by the SOI substrate, resulting in a large process window margin without undesirable parasitic phenomena. The transistors fabricated by the proposed method show higher drive current and better short channel effects than conventionally rapid thermal annealed (RTA) devices.
Keywords :
CMOS integrated circuits; MOSFET; amorphisation; doping profiles; electric current; ion implantation; laser beam annealing; nanotechnology; semiconductor device measurement; silicon-on-insulator; 50 nm; CMOS transistors; SOI CMOS transistors; SOI substrate; Si-SiO/sub 2/; drive current; laser annealing; low energy laser annealing; parasitic phenomena; physical gate length; pre-amorphization implantation; process window margin; rapid thermal annealed devices; short channel effects; transistor fabrication; ultra shallow junction; Boron; Impurities; Laser noise; Laser theory; Optical control; Optical device fabrication; Rapid thermal annealing; Silicon; Substrates; Temperature;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934951
