• DocumentCode
    3262346
  • Title

    A fixed-die floorplanning algorithm using an analytical approach

  • Author

    Zhan, Yong ; Feng, Yan ; Sapatnekar, Sachin S.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA
  • fYear
    2006
  • fDate
    24-27 Jan. 2006
  • Abstract
    Fixed-die floorplanning is an important problem in the modern physical design process. An effective floorplanning algorithm is crucial to improving both the quality and the time-to-market of the design. In this paper, we present an analytical floorplanning algorithm that can be used to efficiently pack soft modules into a fixed die. The locations and sizing of the modules are simultaneously optimized so that a minimum total wire length is achieved. Experiments on the MCNC and GSRC benchmarks show that our algorithm can achieve above a 90% success rate with a 10% white space constraint in the fixed die, and the efficiency is much higher than that of the simulated annealing based algorithms for benchmarks containing a large number of modules.
  • Keywords
    integrated circuit layout; modules; fixed-die floorplanning algorithm; minimum total wire length; simulated annealing; soft modules; Algorithm design and analysis; Design methodology; Manufacturing; Partitioning algorithms; Process design; Runtime; Simulated annealing; Very large scale integration; White spaces; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation, 2006. Asia and South Pacific Conference on
  • Print_ISBN
    0-7803-9451-8
  • Type

    conf

  • DOI
    10.1109/ASPDAC.2006.1594779
  • Filename
    1594779