Title :
High performance sub-60 nm SOI MOSFETs with 1.2 nm thick nitride/oxide gate dielectric
Author :
Maszara, W.P. ; Krishnan, S. ; Xiang, Q. ; Lin, M.-R.
Author_Institution :
Technol. Res. Group, Adv. Micro Devices Inc., Sunnyvale, CA, USA
Abstract :
High performance sub-60 nm SOI CMOS transistors have been developed. An aggressively scaled, 1.2 nm thick, gate dielectric sandwich containing silicon nitride and dioxide layers allowed full control of boron penetration with manageable levels of gate leakage. Excellent values of I/sub dsat/ of 850 /spl mu/A//spl mu/m and 500 /spl mu/A//spl mu/m for NMOS and PMOS were respectively obtained at V/sub dd/=1.2 V and I/sub off/=100 nA//spl mu/m. The CV/I metric was 1.0 and 1.9 ps for NMOS and PMOS respectively.
Keywords :
CMOS integrated circuits; MOSFET; dielectric thin films; leakage currents; semiconductor device measurement; silicon-on-insulator; surface contamination; 1.2 V; 1.2 nm; 60 nm; CV/I metric; NMOSFET; PMOSFET; SOI CMOS transistors; SOI MOSFETs; Si-SiO/sub 2/; Si/sub 3/N/sub 4/-SiO/sub 2/; boron penetration control; drain saturation current; gate dielectric sandwich; gate leakage; nitride/oxide gate dielectric; silicon nitride/dioxide layers; Boron; CMOS technology; Capacitors; Current density; Dielectrics; Gate leakage; MOS devices; MOSFETs; Parasitic capacitance; Silicon;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934952
