DocumentCode

3262362

Title

A Hardware-efficient Architecture For 3-D Graphics Processor

Author

Liang, Bor-Sung ; Nieh, You-Cheng ; Niou, Yih-Pwu ; Jen, Chein-Wei ; Chuang, Gene

fYear

1997

fDate

3-5 June 1997

Firstpage

88

Lastpage

92

Keywords

Acceleration; Buffer storage; Costs; Graphics; Hardware; Pipeline processing; Pixel; Registers; Rendering (computer graphics); Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on

Conference_Location

Taipei, Taiwan

ISSN

1524-766X

Print_ISBN

0-7803-4131-7

Type

conf

DOI

10.1109/VTSA.1997.614735

Filename

614735