Title :
A multi-gate dielectric technology using hydrogen pre-treatment for 100 nm generation system-on-a-chip
Author :
Ono, A. ; Fukasaku, K. ; Hirai, T. ; Makabe, M. ; Koyama, S. ; Ikezawa, N. ; Ando, K. ; Suzuki, T. ; Imai, K. ; Nakamura, N.
Author_Institution :
ULSI Device Dev. Div., NEC Corp., Sagamihara, Japan
Abstract :
A multi-gate dielectric technology using hydrogen pre-treatment has been developed for 100-nm generation CMOS technologies. This process can remove the chemical oxide layer and smoothes the Si surface before gate-oxidation to improve interface carrier mobility as well as reliability of 1.3 nm ultra-thin gate dielectric film. In multi-oxide processing, the hydrogen pretreatment does not affect the performance or yield in the thick gate region (1.6-3.4 nm). Using this technology, we have achieved I/sub D//sup sat/ of 780 /spl mu/A//spl mu/m (I/sub OFF/=25 nA//spl mu/m) and 305 /spl mu/A//spl mu/m (I/sub OFF/=30 nA//spl mu/m) for 70-nm nMOS and pMOS, respectively, with 1.3 nm gate dielectric at 1.0 V operation. In addition to the performance improvement, the reliability in terms of TDDB and NBTI (negative bias temperature instability) were also improved.
Keywords :
CMOS integrated circuits; MOSFET; carrier mobility; dielectric thin films; electric breakdown; hydrogen; integrated circuit reliability; integrated circuit yield; surface topography; surface treatment; thermal stability; 1 V; 1.3 nm; 1.6 to 3.4 nm; 100 nm; CMOS technology; H; NBTI; Si; Si surface smoothing; SiO/sub 2/-Si; TDDB; chemical oxide layer removal; drain saturation current; gate dielectric; gate-oxidation; hydrogen pre-treatment; hydrogen pretreatment; interface carrier mobility; multi-gate dielectric technology; multi-oxide processing; nMOSFET; negative bias temperature instability; operating voltage; pMOSFET; reliability; system-on-a-chip; thick gate region performance; thick gate region yield; ultra-thin gate dielectric film; CMOS technology; Chemical processes; Chemical technology; Degradation; Dielectrics; Hydrogen; Rough surfaces; Surface morphology; Surface roughness; Surface treatment;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934956