Title :
Deep sub-micron CMOS device design for low power analog applications
Author :
Deshpande, H.V. ; Cheng, B. ; Woo, J.C.S.
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
Signal swing, power and device performance requirements for analog applications result in trade-offs for scaled MOSFET design. This paper presents a comprehensive study on optimization of deep sub-micron NMOS device for low power analog applications. It is shown that novel channel engineering is essential along with thin gate oxides and shallow junctions for improving the device analog performance.
Keywords :
CMOS analogue integrated circuits; MOSFET; analogue processing circuits; circuit optimisation; integrated circuit design; low-power electronics; CMOS device design; NMOS device optimization; SiO/sub 2/-Si; analog applications; channel engineering; device analog performance; device performance requirements; low power analog applications; optimization; scaled MOSFET design; shallow junctions; signal power; signal swing; thin gate oxides; 1f noise; Analog circuits; Implants; MOSFET circuits; Noise reduction; Power MOSFET; Power dissipation; Signal design; Threshold voltage; Transconductance;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934960
