A high performance 0.12 /spl mu/m CMOS with manufacturable 0.18 /spl mu/m technology

Author

Ichinose, K. ; Saito, T. ; Yanagida, Y. ; Nonaka, Y. ; Torii, K. ; Sato, H. ; Saito, N. ; Wada, S. ; Mori, K. ; Mitani, S.

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2001

fDate

12-14 June 2001

Firstpage

103

Lastpage

104

Abstract

High-performance 0.12 /spl mu/m CMOS devices with manufacturable 0.18 /spl mu/m technology are presented. A nominal I/sub dsat/N/P of 950/410 /spl mu/A//spl mu/m at an I/sub off/ of 12 nA//spl mu/m is achieved by reducing the body effect. The double-sidewall structure developed can reduce gate-fringe capacitance without increasing the junction leakage, and the inverter delay of 11 ps/stage is achieved at a nominal L/sub gate/ of 0.12 /spl mu/m. Small 6T-SRAM cells of 3.1 /spl mu/m/sup 2/ with 0.5 /spl mu/m gate pitch are implemented using a vertical well isolation and a self-aligned contact (SAC). In the SAC process, a blanket Si/sub 3/N/sub 4/ layer used as an etching stopper is optimized for the I/sub dsat/N/P ratio and the negative bias temperature instability (NBTI) reliability. The 9-level interconnection is optimized to reduce a long wire RC-delay.

Keywords

CMOS integrated circuits; capacitance; circuit stability; delays; electrical contacts; etching; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; isolation technology; leakage currents; logic gates; thermal stability; 0.12 micron; 0.18 micron; 0.5 micron; 11 ps; 6T-SRAM cell; CMOS device performance; CMOS devices; CMOS technology; NBTI reliability; SAC process; Si/sub 3/N/sub 4/; blanket Si/sub 3/N/sub 4/ etch stop layer; body effect; double-sidewall structure; drain saturation N/P ratio; gate length; gate pitch; gate-fringe capacitance; inverter delay; junction leakage; manufacturable technology; multi-level interconnection optimization; negative bias temperature instability reliability; off current; self-aligned contact; vertical well isolation; wire RC-delay; CMOS technology; Capacitance; Delay; Etching; Inverters; Manufacturing; Negative bias temperature instability; Niobium compounds; Titanium compounds; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934970

Filename

934970