A new test and characterization scheme for 10+ GHz low jitter wide band PLL

Author

Miki, Kazuhiko ; Boerstler, David ; Hailu, Eskinder ; Qi, Jieming ; Pettengill, Sarah ; Goto, Yuichi

Author_Institution

Toshiba Corp., Kawasaki

fYear

2006

fDate

24-27 Jan. 2006

Abstract

This paper presents a new test and characterization scheme for 10+ GHz low jitter wide band PLL in 90 nm partially depleted (PD) silicon-on-insulator (SOI) CMOS technology. We measure the frequency range of VCOs without adding any devices for test between charge-pump (CP) and voltage-controlled oscillator (VCO). That test scheme gives us the intermediate frequency of VCO as well as the maximum and the minimum frequency. This paper also describes circuitry to observe the duty cycle of 4.2GHz clock directly on a wafer probe station, including a method to verify the measured duty cycle

Keywords

CMOS integrated circuits; jitter; microwave oscillators; phase locked loops; silicon-on-insulator; voltage-controlled oscillators; 4.2 GHz; CMOS technology; VCO; partially depleted silicon-on-insulator; phase locked loops; voltage-controlled oscillator; wafer probe station; wide band PLL; CMOS technology; Charge pumps; Circuit testing; Current measurement; Frequency measurement; Jitter; Phase locked loops; Silicon on insulator technology; Voltage-controlled oscillators; Wideband;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 2006. Asia and South Pacific Conference on

Conference_Location

Yokohama

Print_ISBN

0-7803-9451-8

Type

conf

DOI

10.1109/ASPDAC.2006.1594793

Filename

1594793