Title :
A cycle accurate power estimation tool
Author :
Chaudhry, Rajat ; Stasiak, Daniel ; Posluszny, Stephen ; Dhong, Sang
Author_Institution :
STI Design Center, IBM Corp., Austin, TX
Abstract :
Power consumption is one of the major challenges in VLSI Design. Power constrained designs need tools to accurately predict the power consumption and provide feedback to designers on the efficiency of the power management logic. In this paper we present the methodology behind a cycle accurate power estimation tool. This tool was used to estimate the power of a first generation CELL Processor. The tool extracts switching and clock activity from RTL simulations and applies them to transistor level macro power models to calculate the power for every cycle of the simulation trace
Keywords :
VLSI; estimation theory; integrated circuit design; low-power electronics; microprocessor chips; RTL simulation; VLSI; clock activity; cycle accurate power estimation tool; first generation CELL Processor; power consumption; switching activity; transistor level macro power model; Capacitance; Clocks; Energy consumption; Energy management; Feedback; Frequency; Leakage current; Logic; Switching circuits; Very large scale integration;
Conference_Titel :
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-9451-8
DOI :
10.1109/ASPDAC.2006.1594795
