High-density and high-performance 6T-SRAM for system-on-chip in 130 nm CMOS technology

Author

Kong, W. ; Venkatraman, R. ; Castagnetti, R. ; Duan, F. ; Ramesh, S.

Author_Institution

LSI Logic Corp., Santa Clara, CA, USA

fYear

2001

fDate

12-14 June 2001

Firstpage

105

Lastpage

106

Abstract

We have developed the smallest high density 6T-SRAM cell (1.87 /spl mu/m/sup 2/) reported to date in 130 nm CMOS logic process for system-on-chip (SOC) applications. We have also developed an ultra-high speed 6T-SRAM cell (2.49 /spl mu/m/sup 2/) with cell current of 116 /spl mu/A for SOC applications requiring even higher performance. These were achieved using our systematic SRAM technology development methodology and optimized OPC capability. These cells do not require additional process steps and use 248 nm lithography, making them very attractive for low-cost SOC manufacturing.

Keywords

CMOS memory circuits; SRAM chips; electric current; integrated circuit design; proximity effect (lithography); ultraviolet lithography; very high speed integrated circuits; 116 muA; 130 nm; 248 nm; 6T-SRAM; CMOS logic process; CMOS technology; SOC applications; SOC manufacturing; SOC manufacturing cost; SRAM technology development methodology; UV lithography; cell current; high density 6T-SRAM cell; optimized OPC capability; system-on-chip; ultra-high speed 6T-SRAM cell; CMOS logic circuits; CMOS process; CMOS technology; Etching; Isolation technology; Lithography; Manufacturing processes; Optimization methods; Random access memory; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934971

Filename

934971