Title :
Scalability and biasing strategy for CMOS with active well bias
Author :
Shih-Fen Huang ; Wann, C. ; Yu-Shyang Huang ; Chih-Yung Lin ; Schafbauer, T. ; Shui-Ming Cheng ; Yao-Ching Cheng ; Vietzke, D. ; Eller, M. ; Chuan Lin ; Quiyi Ye ; Rovedo, N. ; Biesemans, S. ; Nguyen, P. ; Dennard, R. ; Bomy Chen
Author_Institution :
Semicond. R&D Center, IBM Corp., Hopewell Junction, NY, USA
Abstract :
We analyze the scalability of the two well bias strategies: reverse bias to reduce standby power, and forward bias to improve the speed or to reduce active power. We then present the device design space that includes well bias as an integral part of the design variables following the SIA Roadmap specifications. We show that proper well biases are needed for bulk CMOS just to continue to meet the SIA Roadmap requirements for performance and standby current. The scalabilities for forward bias and reverse bias are different. The advantage of reverse bias is diminishing with scaling due to low initial V/sub t/ values, short-channel effects, and band-to-band tunneling. The advantage of the forward body bias is preserved better with scaling due to high initial V/sub t/ values as well as smaller depletion width, and increases with V/sub t/ nonscaling. The forward bias approach is not effective in speed improvement for ultra-high performance applications with high V/sub dd/ overdrive and low V/sub t/ to start with, but is effective in active power reduction at a fixed speed target.
Keywords :
CMOS integrated circuits; integrated circuit design; low-power electronics; tunnelling; CMOS; SIA Roadmap specifications; active power; active power reduction; active well bias; band-to-band tunneling; biasing strategy; bulk CMOS; chip speed; depletion width; design variables; device design space; fixed speed target; forward bias; forward body bias; reverse bias; scalability; short-channel effects; speed improvement; standby power; threshold voltage; ultra-high performance applications; well bias; well bias strategy; CMOS technology; Delay; MOSFET circuits; Microelectronics; Performance gain; Research and development; Scalability; Space technology; Tin; Tunneling;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934972