A fully planarized 8M bit ferroelectric RAM with ´chain´ cell structure

Author

Ozaki, Takashi ; Iba, J. ; Kanaya, Haruichi ; Morimoto, Takuya ; Hidaka, O. ; Taniguchi, Ayako ; Kumura, Yusuke ; Yamakawa, Kiyoshi ; Oowaki, Yukihito ; Kunishima, I.

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

2001

fDate

12-14 June 2001

Firstpage

113

Lastpage

114

Abstract

A 8M-bit fully functional ferroelectric RAM (FeRAM) with 0.25 /spl mu/m CMOS process was successfully fabricated by using a highly reliable Pt-SRO-PZT-SRO-Pt stacked capacitor and aluminum reflow based low damage metallization process. The chip area of 76 mm/sup 2/ was achieved by using a ´chain´ cell structure.

Keywords

CMOS memory circuits; ferroelectric capacitors; ferroelectric storage; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; surface topography; 0.25 micron; 8 Mbit; CMOS process; FeRAM; Pt-SrRuO/sub 3/-PZT-SrRuO/sub 3/-Pt; Pt-SrRuO3-PbZrO3TiO3-SrRuO3-Pt; aluminum reflow based low damage metallization process; chain cell structure; ferroelectric RAM; planarized ferroelectric RAM; reliable Pt-SRO-PZT-SRO-Pt stacked capacitor; Aluminum; CMOS technology; Capacitors; Electrodes; Ferroelectric films; Ferroelectric materials; Filling; Metallization; Nonvolatile memory; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-89114-012-7

Type

conf

DOI

10.1109/VLSIT.2001.934975

Filename

934975