A Communications-inspired SOC Design Paradigm for Extending Moore´s Law into the Nanometer Era

This seminar will focus on a key barrier to the continuation of Moore´s Law in the nanometer regime: the power-reliability wall. Power and reliability though intimately intertwined have historically been addressed by disparate communities. The result being the above mentioned power-reliability wall which threatens the well-being of the semiconductor industry. I will describe a communications-inspired design paradigm for nanometer ICs that has the potential to breach the power-reliability wall. This paradigm is based on the view that nanometer SOCs are miniature communication networks; a view first proposed in our 1997 publication and later in the 1999 and 2003 International Technology Roadmap Semiconductors. The talk will demonstrate communications-inspired designs of on-chip computation and communication sub-systems.