Title :
Performance and reliability of ultra thin CVD HfO/sub 2/ gate dielectrics with dual poly-Si gate electrodes
Author :
Lee, S.J. ; Luan, H.F. ; Lee, C.H. ; Jeon, T.S. ; Bai, W.P. ; Senzaki, Y. ; Roberts, D. ; Kwong, D.L.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
MOSFETs with high quality ultra thin (EOT/spl sim/10.3 /spl Aring/) HfO/sub 2/ gate stacks and self-aligned dual poly-Si gate are fabricated and characterized. Both n- and p-MOSFETs show good electron and hole mobility, respectively, and excellent sub-threshold swings. In addition, the HfO/sub 2/ gate stack exhibits excellent thermal stability with poly-Si gates up to 1050/spl deg/C/30 s gate activation annealing and shows excellent TDDB reliability characteristics with negligible charge trapping and SILC under high-field stressing.
Keywords :
MOSFET; dielectric thin films; electron mobility; elemental semiconductors; hafnium compounds; hole mobility; leakage currents; rapid thermal annealing; semiconductor device breakdown; semiconductor device reliability; semiconductor device testing; silicon; thermal stability; 10.3 angstrom; 1050 C; 30 s; EOT; MOSFETs; SILC; Si-HfO/sub 2/-Si; TDDB reliability; charge trapping; dual poly-Si gate electrodes; electron mobility; equivalent oxide thickness; gate activation annealing; high-field stressing; hole mobility; n-MOSFETs; p-MOSFETs; poly-Si gates; reliability; self-aligned dual poly-Si gate; sub-threshold swing; thermal stability; ultra thin CVD HfO/sub 2/ gate dielectrics; ultra thin HfO/sub 2/ gate stacks; Annealing; Capacitance-voltage characteristics; Charge carrier processes; Dielectrics; Electrodes; Electron mobility; Hafnium oxide; Leakage current; MOSFET circuits; Thermal stability;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934985
