Title :
Optimization of annealing conditions for dual damascene Cu microstructures and via chain yields
Author :
Qing-Tang Jiang ; Frank, Andreas ; Havemann, R.H. ; Parihar, V. ; Nowell, M.
Abstract :
The effect of different post electroplating anneals on dual damascene Cu microstructures and via chain yields using both rapid thermal processing and furnace anneal were investigated. It was found that the grain size, [111] texture, Cu line resistance, and dual damascene Cu via chain yields varied strongly with the annealing conditions. The minimum feature size of trench width or height imposes physical limits on the average grain size. Via chain yield failure analysis was also carried out using SEM cross sections.
Keywords :
annealing; copper; electroplating; failure analysis; grain size; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; integrated circuit yield; optimisation; rapid thermal annealing; scanning electron microscopy; texture; Cu; Cu [111] texture; Cu line resistance; SEM cross sections; annealing conditions; annealing conditions optimization; average grain size; dual damascene Cu microstructures; dual damascene Cu via chain yields; furnace anneal; grain size; minimum feature size; post electroplating anneals; rapid thermal processing; trench height; trench width; via chain yield failure analysis; via chain yields; Displays; Failure analysis; Furnaces; Grain size; Instruments; Microstructure; Rapid thermal annealing; Rapid thermal processing; Scanning electron microscopy; Temperature;
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
DOI :
10.1109/VLSIT.2001.934988