DocumentCode :
3262973
Title :
Impact of vias on the thermal effect of deep sub-micron Cu/low-k interconnects
Author :
Ting-Yen Chiang ; Saraswat, K.C.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fYear :
2001
fDate :
12-14 June 2001
Firstpage :
141
Lastpage :
142
Abstract :
This paper investigates in detail the impact of vias on the thermal characteristics of high performance Cu/low-k interconnects. It shows that the effectiveness of vias in reducing the temperature rise in interconnects is highly dependent on the dielectric material used. An efficient 3D electro-thermal simulation methodology is presented to evaluate the temperature profile along wires and the thermal coupling between them. The possibility that the thermal effect may degrade the expected speed improvement from the use of low-k dielectrics is discussed. Finally, the more realistic RC performances of various low-k schemes, under the impact of thermal effects, are examined.
Keywords :
circuit simulation; copper; dielectric thin films; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; permittivity; temperature distribution; thermal analysis; 3D electro-thermal simulation methodology; Cu; Cu/low-k interconnects; RC performance; dielectric material; interconnect temperature rise; low-k dielectrics; speed improvement degradation; temperature profile; thermal characteristics; thermal coupling; thermal effect; via effectiveness; vias; Capacitance; Current density; Dielectrics; Integrated circuit interconnections; Polymers; Temperature; Thermal conductivity; Thermal resistance; Transient analysis; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
4-89114-012-7
Type :
conf
DOI :
10.1109/VLSIT.2001.934989
Filename :
934989
Link To Document :
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