Time domain black-box modelling of CMOS structures and analog timing simulation

A new macromodeling procedure for CMOS LSI circuits is proposed. Problems concerned with transient properties of the macromodel are explored and solved. The macroanalysis is performed at gate level, the level most frequently used for logic simulation. However, the accuracy of the model used for macroanalysis is still better so that these two types of network verification do not exclude each other. The problem of propagation-delay modeling is solved by implementation of an analog controlled voltage source, while the problem of output resistance modeling is solved by a resistor whose value is controlled by the output voltage