Title :
An interface between VHDL and EDIF
Author_Institution :
CAD Language Syst. Inc., Rockville, MD, USA
fDate :
Feb. 29 1988-March 3 1988
Abstract :
The VHSIC hardware description language (VHDL) and the electronic design interchange format (EDIF) are industry standards for describing design data. The author examines the application range of each standard and the way each standard relates to the other. He discusses the motivation for relating VHDL and EDIF, as well as scenarios in which VHDL and EDIF can contribute to different aspects of the design process.<>
Keywords :
specification languages; standards; EDIF; VHDL; VHSIC hardware description language; design data; electronic design interchange format; industry standards; interface; Computer aided manufacturing; Design automation; Documentation; Electronics industry; Fabrication; Hardware design languages; Industrial electronics; Layout; Process design; Very high speed integrated circuits;
Conference_Titel :
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-0828-5
DOI :
10.1109/CMPCON.1988.4881
