Low-power digital signal processor design for a hearing aid

Author

Shaer, Lama ; Nahlus, Ihab ; Merhi, Jawad ; Kayssi, Ayman ; Chehab, Ali

Author_Institution

Dept. of Electr. & Comput. Eng., American Univ. of Beirut, Beirut, Lebanon

fYear

2013

fDate

16-18 Dec. 2013

Firstpage

40

Lastpage

44

Abstract

A new low-power digital signal processor (DSP) design for a hearing aid system is proposed. A stochastic method was applied to the DSP in order to fulfill the needs of the hearing aid system, considered to be an error-tolerant system. The different blocks that form the DSP are presented in this paper. The implementation and layout were performed and simulated using a 90 nm CMOS process. Simulation results showed excellent energy consumption savings in the range of 4.5x to 10x of the proposed DSP design when compared to similar DSPs.

Keywords

CMOS integrated circuits; biomedical electronics; digital signal processing chips; hearing aids; integrated circuit layout; low-power electronics; stochastic processes; CMOS process; DSP; energy consumption saving; error-tolerant system; hearing aid system; low-power digital signal processor design; size 90 nm; stochastic method; Auditory system; Digital signal processing; Energy consumption; Filter banks; Finite impulse response filters; Power demand; digital signal processor; energy consumption; error-tolerant; hearing aid system; low power; stochastic;

fLanguage

English

Publisher

ieee

Conference_Titel

Energy Aware Computing Systems and Applications (ICEAC), 2013 4th Annual International Conference on

Conference_Location

Istanbul

Type

conf

DOI

10.1109/ICEAC.2013.6737634

Filename

6737634