DocumentCode

3263394

Title

Bit-serial Systolic Array Implementation Of Euclid´s Algorithm For Inversion And Division In GF(2/supm)

Author

Guo, Jyh-Huei ; Wang, Chin-Liang

fYear

1997

fDate

3-5 June 1997

Firstpage

113

Lastpage

117

Keywords

Bidirectional control; Circuits; Computer architecture; Cryptography; Delay; Fault tolerance; Hardware; Inverters; Systolic arrays; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on

Conference_Location

Taipei, Taiwan

ISSN

1524-766X

Print_ISBN

0-7803-4131-7

Type

conf

DOI

10.1109/VTSA.1997.614740

Filename

614740