Title :
Bit-serial Systolic Array Implementation Of Euclid´s Algorithm For Inversion And Division In GF(2/supm)
Author :
Guo, Jyh-Huei ; Wang, Chin-Liang
Keywords :
Bidirectional control; Circuits; Computer architecture; Cryptography; Delay; Fault tolerance; Hardware; Inverters; Systolic arrays; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1997. Proceedings of Technical Papers. 1997 International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
0-7803-4131-7
DOI :
10.1109/VTSA.1997.614740
