Title :
An online RTL-level scan-chain-based methodology for accelerating IP emulation debugging at run-time
Author_Institution :
Mentor Graphics, Cairo, Egypt
Abstract :
In this paper, an online RTL-level scan chain methodology is proposed to reduce debugging time, effort and accelerate IP emulation. Run-time changes of the values of the signals of the IP during execution-time can be done by the proposed scan-chain methodology. A utility tool was developed to help ease this process. Our experiment shows that, the area overhead is neglected compared to the gained performance benefits. But, design requires more compilation time.
Keywords :
electronic engineering computing; logic circuits; logic testing; microprocessor chips; debugging time; execution time; online RTL-level scan-chain-based methodology; run-time IP emulation debugging acceleration; utility tool; Acceleration; Debugging; Emulation; Hardware; Hardware design languages; IP networks; System-on-chip; Debugging; Emulation; HDL; RTL; Run-Time; Scan-Chain;
Conference_Titel :
Energy Aware Computing Systems and Applications (ICEAC), 2013 4th Annual International Conference on
Conference_Location :
Istanbul
DOI :
10.1109/ICEAC.2013.6737649
