Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout

Author

Dae Hyun Kim ; Athikulwongse, Krit ; Sung Kyu Lim

Author_Institution

Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA

Volume

21

Issue

5

fYear

2013

fDate

May-13

Firstpage

862

Lastpage

874

Abstract

The technology of through-silicon vias (TSVs) enables fine-grained integration of multiple dies into a single 3-D stack. TSVs occupy significant silicon area due to their sheer size, which has a great effect on the quality of 3-D integrated chips (ICs). Whereas well-managed TSVs alleviate routing congestion and reduce wirelength, excessive or ill-managed TSVs increase the die area and wirelength. In this paper, we investigate the impact of the TSV on the quality of 3-D IC layouts. Two design schemes, namely TSV co-placement (irregular TSV placement) and TSV site (regular TSV placement), and accompanying algorithms to find and optimize locations of gates and TSVs are proposed for the design of 3-D ICs. Two TSV assignment algorithms are also proposed to enable the regular TSV placement. Simulation results show that the wirelength of 3-D ICs is shorter than that of 2-D ICs by up to 25%.

Keywords

integrated circuit layout; three-dimensional integrated circuits; 2D IC; 3D integrated chips; 3D stacked IC layout; TSV assignment algorithms; TSV coplacement; TSV site; TSV technology; ill-managed TSV; irregular TSV placement; multiple dies; regular TSV placement; single 3D stack; through-silicon-via impact; wirelength reduction; Algorithm design and analysis; Force; Layout; Logic gates; Routing; Through-silicon vias; 3-D integrated chip (IC); interconnect; placement; routing; through-silicon via (TSV);

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2012.2201760

Filename

6268361