Temporal proof of the behavior of sequential machines

The methodology presented in this paper concerns formal modeling and verification of discrete systems. Indeed, the behavior of a system, which needs to be analyzed, is described thanks to a finite state machine based model. Translating the behavior of such a model into a formal system then allows us to carry out some proofs of properties. In order to take time into account, temporal logic has been chosen. Using this formal framework, it is possible to formally manipulate a set of temporal logic formulae which represent the system in order to verify that the system fulfils some requirements (concerning security, quality, etc.) which can be expressed as temporal logic formulae. It has been necessary to develop a formal tool for proving some of these properties which need to study the influence of the present situation on the future evolution of the system: the Temporal Boolean Difference