DocumentCode
3264128
Title
Selective Placement Data Cache for Low Energy Embedded System
Author
Raveendran, Biju K. ; Sudarshan, T.S.B. ; Gurunarayanan, S.
Author_Institution
Comput. Sci. Group, Pilanijndia
fYear
2006
fDate
20-23 Dec. 2006
Firstpage
473
Lastpage
476
Abstract
This paper proposes a process aware selective placement scheme for N-way set associative cache with the help of a victim set. In this work, we consider the data cache subsystem, as it is one of the most power consuming microarchitectural parts of an embedded system and set associative cache, being one of the popular mapping schemes for data cache. We propose a selective placement scheme to reduce tag comparison and power consumption using victim set. We show that, this scheme has reduced the tag comparison by 70% and power saving by 72% as compared to conventional caching scheme. Experimental results are obtained using Simplescalar 2.0 cache simulator for SPEC95benchmark suite.
Keywords
cache storage; computer architecture; content-addressable storage; embedded systems; low-power electronics; N-way set associative cache; data cache subsystem; low energy embedded system; microarchitecture; power consumption; process aware selective placement scheme; tag comparison; victim set; Application software; Cache memory; Computer architecture; Computer science; Embedded system; Energy consumption; Energy efficiency; Instruments; Microarchitecture; Phased arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Computing and Communications, 2006. ADCOM 2006. International Conference on
Conference_Location
Surathkal
Print_ISBN
1-4244-0716-8
Electronic_ISBN
1-4244-0716-8
Type
conf
DOI
10.1109/ADCOM.2006.4289938
Filename
4289938
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