On hardware architecture and processing order of HEVC intra prediction module

This article presents a parallel and memory optimized hardware architecture for intra prediction of the High Efficiency Video Coding (HEVC) standard. The architecture consists of 64 parallel reconfigurable Processing Elements as datapaths and supports all 35 intra prediction modes and all prediction sizes from 4×4 to 64×64. In order to avoid implementing large area memory-datapaths interconnections and save memory usage, the maximum number of reference registers is reduced from 129 to 72 by reclassifying 35 prediction modes into 3 general categories. In addition, a 3 stage hierarchical processing order including an S-shaped scan order of blocks and a Bidirectional Ring Register File is proposed to avoid bandwidth bottleneck and increase system throughput. This architecture is synthesized using TSMC 130nm technology and the working frequency is up to 400MHz with 324K gates area. Running at 300MHz, it supports real time 1080p@60fps full modes and full sizes HEVC intra prediction.