An instruction set extension for java bytecodes translation acceleration

Java has become popular in a wide range of applications. Just-in-time translation is crucial for providing efficient execution of Java programs. This paper presents an architecture extension to RISC processors that accelerates Java bytecodes translation. Our results show that the incorporation of this technique in a 4-way superscalar RISC and in one high performance embedded processor gives an average speedup of 2.95x and 2.29x respectively. A first order approximation using ASIC synthesis tools shows that this acceleration is performed with only a small increase in hardware.