Title :
A state-of-the-art VHDL simulator
Author :
Coelho, David R. ; Stanculescu, Alec G.
fDate :
Feb. 29 1988-March 3 1988
Abstract :
The VHDL language has considerably more features than most other hardware description languages to enable it to be effective over a wide range of uses. One of the concerns that emerges is whether an efficient implementation of VHDL can be achieved while still maintaining a full language implementation. This question is addressed, and the results that have been achieved in the implementation of a state-of-the-art VHDL simulator are summarized.<>
Keywords :
CAD; digital simulation; specification languages; standards; VHDL language; hardware description languages; state-of-the-art VHDL simulator; Analytical models; Fabrication; Graphics; Hardware design languages; Logic design; Logic gates; Process design; Propagation delay; Standards organizations; Timing;
Conference_Titel :
Compcon Spring '88. Thirty-Third IEEE Computer Society International Conference, Digest of Papers
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-8186-0828-5
DOI :
10.1109/CMPCON.1988.4882
